The present invention relates to integrated circuits, and more particularly to a circuit for rectifying and integrating a signal relative to an intermediate reference voltage for outputting a rail-to-rail signal.
Rectifying and integrating circuits for an alternating input voltage with respect to a reference voltage are used in many applications, and are included in many commercially available devices. A rectifying integrator circuit may be formed, as depicted in the basic scheme of FIG. 1a, by a rectifier connected in cascade to an integrator stage and a SampleandHold stage. FIG. 1b is a graph illustrating the main signals of the rectifying integrator illustrated in FIG. 1a. 
By using these three blocks alone it is possible to obtain an output voltage that varies between the voltage reference (Vref) and the maximum or the minimum input voltage, with a reduced dynamic range, rather than between the minimum and the maximum input voltage, as would be preferred. In particular, if the voltage reference corresponds to an intermediate value between the maximum and minimum input voltage Vin, the dynamic range of the output voltage is practically halved if compared to the maximum input dynamic range.
This drawback may be averted by placing in cascade to the three above mentioned blocks an output stage having a gain value equal to two and which also functions as a level shifter, thus obtaining an output voltage Vout with a full dynamic range. The disadvantage of this approach is that a gain stage placed at the end of the cascade lowers the signal/noise ratio.
This problem may be overcome by the use of a switched-capacitor integrator as shown in FIG. 2a, which also functions as a rectifier and level shifter. FIG. 2b is a graph illustrating the main signals of the switched-capacitor rectifier illustrated in FIG. 2a. The input voltage Vin is sampled on the capacitor C1 with respect to the voltage reference Vref. The switches driven by the driving phases "PHgr"2a and "PHgr"2b of FIG. 2a connect the node of the capacitor C1 at the lowest potential to the inverting node of the operational amplifier, while the other node of the capacitor is connected to a common ground node Vgnd. Hence, the integration and rectification of the input voltage are carried out simultaneously because the integrating capacitor C2 is always charged with voltages of the same sign, regardless of whether Vin is higher or lower than Vref.
The circuit of FIG. 2a provides for an output voltage with a full dynamic range, however there are two drawbacks. A first drawback is that the operational amplifier of the integrator functions with an input connected to ground Vgnd that is at the lowest voltage, thus originating imprecisions in presence of relatively small input signals.
A second drawback is that the switches exhibit parasitic capacitances which, when discharged, produces currents in opposition to the integrating current. This brings a below ground potential to the inverting input of the operational at the start of each half-period of integration.
In view of the foregoing background, it is an object of the present invention to provide a rectifying integrator for producing a full dynamic output voltage.
This and other objects, advantages and features of the present invention are provided by a rectifying integrator comprising a pair of integrators, both referenced by an intermediate voltage reference within the dynamic voltage range of the input signal, and which are coupled to a pair of respective hold capacitors. The hold capacitors respectively integrate the part of the input signal that either exceeds the voltage reference or remains below the voltage reference. The voltages on the hold capacitors are eventually combined to produce the desired output voltage.
Preferably, the two integrators are combined in a unique integrating stage that is formed according to an offset recovery switched-capacitance technique, using two integrating capacitors coupled to respective hold capacitors at the output of a single amplifier. The hold capacitors are alternately connected to the integration feedback line of the amplifier depending on whether the input voltage exceeds or remains below the voltage reference. The voltages on the hold capacitors which are respectively higher or lower than the voltage reference, are input to a voltage adder which produces an output voltage Vout corresponding to the difference between the voltages present on the two hold capacitors.